A Low Power DDR SDRAM Controller Design

This paper work leads to a working implementation of a Low Power DDR SDRAM Controller that is meant to be used as a reference for future implementations. . The DDR SDRAM is an enhancement to the traditional Synchronous DRAM. It supports data transfers on both edges of each clock cycle, effectively doubling the data throughput of the memory device. In this project Low Power Techniques are proposed for DDR SDRAM Controller and which is implemented with 180nm CMOS Technology by using Cadence tools. The proposed controller performance is evaluated at a clock rate of 133MHz, 64-bit data changing at both clock edges with a burst length of 4 and with read CAS (Column Address strobe) latency 2. In order to implement proposed DDR SDRAM Memory Controller, the hardware design flow starts with modeling the design using Verilog HDL code, simulated by using Cadence NC Simulator, synthesized by making use of RTL Compiler. Keywords— Column address strobe, Dual data rate (DDR), Synchronous dynamic RAM.